1. Field of the Invention
The present invention relates to an improved bus bridge which enables concurrent access to an I/O bus and a system bus in a multiprocessor system.
2. Description of the Related Art
In a multiprocessor system, all of the processors in the system share a common system bus and a common I/O bus. This common bus architecture restricts both the system bus and the I/O bus to a single transfer at a time. An I/O bus bridge links the system bus to the I/O bus. Therefore, when one processor is communicating with the system or I/O bus, the other processors are either busy with their own internal operations or are waiting for the system and I/O buses to become free. The time that the processor spends waiting for the buses to become available is referred to as bus latency.
In a conventional multiprocessor, common-bus architecture, during an I/O request, the system bus is actually needed only for a short time to transfer the requested address from the processor to the I/O bus bridge. However, the bus bridge holds the system bus idle for the entire data transfer. An I/O controller on the I/O bus latches the address from the I/O bus bridge and handles the request. The data transfer time may be quite long depending upon the access time of the I/O device. When the I/O cycle is complete, both the system bus and the I/O bus will become available to the other processors.
During the period that one processor is using the I/O bus, the bus bridge holds the system bus idle; and the other processor must wait for the buses to become available to initiate any type of data transfer. As the number of processors increases, the number of bus accesses increases, and, therefore, the bus latency increases. Inherent in typical bus architectures are periods of time when the I/O bus is being accessed and the system bus is being held idle while it awaits the completion of the I/O cycle. During this time, the requesting processor is not using the system bus. Rather, the requesting processor holds the system bus to prevent other processors from accessing the system bus until it receives a reply from the I/O bus indicating the completion of the I/O cycle. The time that the system bus is held but not active while waiting for the I/O cycle to be completed is a principal cause of bus latency in multiprocessor systems.
In order to cut down on the idling time of the system bus, a protocol needs to be developed to prevent any new I/O level transactions from occurring, while enabling system bus level transactions to occur. One possible solution would be to use a "back-off" operation to cancel any I/O requests that have started once a transaction on the I/O bus has begun, thereby releasing the system bus for memory and processor-to-processor transfers. The problem is that some I/O buses, such as EISA bus, do not allow for a graceful "back-off" operation. The only "back-off" operation provided by the EISA bus would result in the receipt of an error condition by the requesting processor which is not desirable.
If the I/O bus does not provide for a graceful back-off as in the case of the EISA bus, the only other solution would be to "back-off" the system bus. However, in a multiprocessor system it is only desirable to "back-off" the processor that is attempting to access the I/O bus and to allow the other processors on the system bus to proceed. Therefore having a single back-off signal would "back-off" the entire system bus. "Backing off" the entire bus would not solve the bus latency problem and would generate additional problems.
Another option would be to generate a "back-off" signal for each processor on the I/O bus bridge. In this case, N number of pins would have to be added to the bus bridge to send an individual back-off signal to each of N number of processors. A common number of processors in a multiprocessor system is 5-8 processors thus 5-8 pins would have to be added to the I/O bus bridge on average. A typical bus bridge is a pin limited circuit, i.e., there are not many extra pins available to add output signals. Additionally, logic would have to be added to the bus bridge for each back-off signal that needs to be controlled. These added complexities do not make it an optimal solution. Furthermore, if the I/O bus bridge allows data to be cached, the cache coherency protocol makes it very difficult to initiate a back-off protocol. Once a request is initiated, other processor modules may be snooping their caches and once snooped cannot be "unsnooped." Thus, the simple back-off protocol used in a single processor system is not an optimal solution for a multiprocessor system.
Another factor contributing to latency in a multiprocessor system is that most I/O buses are slower than system buses. For example, a common multiprocessor system bus runs at 25 MHz and is 64 bits wide. A common I/O bus, such as EISA bus, runs at 8 MHz and is only 32 bits wide. Therefore, a typical system bus can transfer data at a rate of 200 MBytes/sec. An EISA bus can only transfer data at 33 MBytes/sec. Therefore, the system bus is held for a long period of usable bus time while data is transferred from the I/O bus to the system by the slower data rate and lesser bit width of the I/O bus. The time period that the faster system bus is forced to wait for the slower bus to complete its transaction wastes the speed and efficiency that is available from the system bus and is a contributing factor to the system bus latency.
Therefore there exits a need in multiprocessor systems to decrease the bus latency caused by system bus idling during I/O bus transactions and lengthy I/O data transfers.